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The thermo-elastic strain is induced by through silicon vias (TSV) due to the difference of thermal expansion coefficients between the copper (18 ppm °C) and silicon (2.8 ppm °C) when the structure is exposed to a thermal ramp budget in the three dimensional integrated circuit (3DIC) process. These thermal expansion stresses are high enough to introduce the delamination on the interfaces between the copper, silicon, and isolated dielectric. A compact analytic model for the strain field induced by different layouts of thermal copper filled TSVs with the linear superposition principle is found to have large errors due to the strong stress interaction between TSVs. In this work, a nonlinear stress analytic model with different TSV layouts is demonstrated by the finite element method and the analysis of the Mohr's circle. The characteristics of stress are also measured by the atomic force microscope-raman technique with nanometer level space resolution. The change of the electron mobility with the consideration of this nonlinear stress model for the strong interactions between TSVs is ∼2–6% smaller in comparison with those from the consideration of the linear stress superposition principle only.


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