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Self-assembly SiO nanosphere monolayer template is utilized to fabricate nanopatterned sapphire substrates (NPSSs) with 0-nm, 50-nm, and 120-nm spacing, receptively. The GaN growth on top of NPSS with 0-nm spacing has the best crystal quality because of laterally epitaxial overgrowth. However, GaN growth from pattern top is more difficult to get smooth surface than from pattern bottom. The rougher surface may result in a higher work voltage. The stimulation results of finite-difference time-domain (FDTD) display that too large or too small spacing lead to the reduced light extracted efficiency (LEE) of LEDs. Under a driving current 350 mA, the external quantum efficiencies (EQE) of GaN-based LEDs grown on NPSSs with 0-nm, 50-nm, and 120-nm spacing increase by 43.3%, 50.6%, and 39.1%, respectively, compared to that on flat sapphire substrate (FSS). The optimized pattern spacing is 50 nm for the NPSS with 600-nm pattern period.


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