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/content/aip/journal/adva/5/11/10.1063/1.4935749
2015-11-10
2016-09-25

Abstract

High-κ TiO thin films have been fabricated from a facile, combined sol – gel spin – coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO with a small grain size of 18 nm. The refractive index ‘n’ quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 Å. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO were studied by capacitance – voltage (C – V) and deep level transient spectroscopy (DLTS). The flat – band voltage (V) and the density of slow interface states estimated are – 0.9, – 0.44 V and 5.24×1010, 1.03×1011 cm−2; for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross – sections measured by DLTS are E + 0.30, E – 0.21 eV; 8.73×1011, 6.41×1011 eV−1 cm−2 and 5.8×10−23, 8.11×10−23 cm2 for the NMOS and PMOS structures, respectively. A low value of interface state density in both P- and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent.

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