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Very low bias stress in n-type organic single-crystal transistors
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19.The best fits were calculated using the MINUIT code (Ref. 18) by minimizing χ2 on logarithmic sub-sets (nine points per decade: t = 0.1, 0.2, 0.3 s, …, 1, 2, 3 s, …, 10, 20, 30 s, …) of the experimental data.
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FIG. 1.

(a) Output curves (VGS  = 0, 10, …, 80 V) of a PDIF-CN2 single-crystal transistor measured in vacuum. An optical microscope image of one of the bottom gate, bottom contact devices studied is shown in (b)—the scale bar is 200 μm long. From the transfer curve measured in the linear regime (VDS  = 10 V), we extract a threshold voltage VTh of +10 V (c) and an onset voltage VON of −4 V (d). The inset of (c) shows the field-effect mobility versus gate voltage VGS .

Image of FIG. 2.

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FIG. 2.

(a) Normalized source-drain current IDS (t)/I0 of the device whose data are shown in Fig. 1, measured as a function of time in air (blue squares) and in vacuum (green circles) for a 2.5 h period (VGS  = 80 V; VDS  = 10 V). (b) Transfer curves of the device measured before (full symbols) and after (empty symbols) bias stress in air (triangles) and in vacuum (circles). The data show that the bias stress induced decrease of source drain current is due to a small shift in threshold voltage, with the mobility remaining unaffected. (c) Semi-log plot of the current decrease of the same device stressed in vacuum over a period of 3 × 105 s (approximately 3.5 days). After about 2 days, the current tends to saturate, and small changes of the ambient conditions cause changes in the current that are larger than those induced by stressing. The arrows in the inset of (c) mark the current peaks spaced by approximately 24 h, which is indicative of the change in the temperature of the environment.

Image of FIG. 3.

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FIG. 3.

Semi-log plots of the normalized current (IDS (t)/I0 ) measured in air (a) up to 6 × 105 s (∼1 week) while stressing at VGS  = 80 V (VDS  = 10 V) and the same measurements in vacuum (b) up to 105 s (∼28 h), before the saturation shown in Fig. 2(c). The dashed lines are the best fits to the stretched exponential model. The time constants τ extracted from the fits are 1.9 ± 0.2 × 109 s in air and 4.7 ± 0.6 × 109 s in vacuum. The same data are shown in linear scale in the insets to show the characteristic time dependence of the bias stress.

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/content/aip/journal/apl/100/13/10.1063/1.3698341
2012-03-26
2014-04-20

Abstract

Bias stress effects in n-channel organic field-effect transistors(OFETs) are investigated using N,N′-bis(n-alkyl)-(1,7 and 1,6)-dicyanoperylene-3,4:9,10-bis(dicarboximide)s (PDIF-CN2) single-crystaldevices with Cytop gate dielectric, both under vacuum and in ambient. We find that the amount of bias stress is very small as compared to all (p-channel) OFETs reported in the literature. Stressing the PDIF-CN2devices by applying 80 V to the gate for up to a week results in a decrease of the source drain current of only ∼1% under vacuum and ∼10% in air. This remarkable stability of the devices leads to characteristic time constants τ, extracted by fitting the data with a stretched exponential—that are τ ∼ 2 × 109 s in air and τ ∼ 5 × 109 s in vacuum—approximately two orders of magnitude larger than the best values reported previously for p-channel OFETs.

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Scitation: Very low bias stress in n-type organic single-crystal transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/13/10.1063/1.3698341
10.1063/1.3698341
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