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An FESEM image (a) and a magnified FESEM image (b) of as-synthesized CdS nanowires; (c) an HRTEM image of a typical CdS NW and the corresponding SAED pattern recorded along the [-24-23].
Schematic illustrations with top-view (a) and cross-sectional view (b) of as-fabricated CdS NW E-mode FET; (c) top-view FESEM image of an as-fabricated device.
(a) Typical I DS-V DS curves for the CdS NW E-mode FETs with V G changing from 0.4 to 1.6 V stepped by 0.1 V. The arrow indicates the V G increasing direction; (b) corresponding I DS-V G curve with V DS = 1 V. The threshold voltage of the FET is 1 V; The inset is the drain current and the gate leakage current vs V G in the linear scale. (c) The I-V curve measured between a In/Au and an Au electrodes on a CdS NW, which exhibits a typical Schottky junction behavior.
(a) The energy band diagrams of Au and CdS before contacting; the energy band diagrams of Au and CdS in the E-mode FET, which works at V G = 0 (off-state) (b), V G < 0 V (off-state) (c), and V G > V th (on-state) (d). Corresponding equivalent circuits are plotted in the respective figures.
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