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Id-Vg of 1.1 nm EOT HfO2/TiN PMOS and NMOS FETs with various low-temperature anneals and selective metal cladding layers. Employing a 450 °C 10% O2/N2 post-TiN anneal with a W-cladding layer allows for a PMOS Vt = −0.20 V. Using Al-cladding with no post-TiN anneal gives an NMOS Vt = 0.08 V.
Flatband voltage (Vfb) vs. EOT plots for the HfO2/TiN gate stacks with different post-TiN anneals and cladding layers. The left axis displays the extracted EWF for each set of devices.
Backside DSIMS data of metal cladding concentration. During FGA, the Al-cladding diffuses through the unoxidized TiN, reaching the HfO2/TiN interface setting a low NMOS EWF. The Al migration is significantly suppressed through oxidized TiN. The W-cladding does not migrate to the HfO2/TiN interface.
TiN/SiO2 gate stacks exhibit EWF shifts of ∼400 meV after 450 °C O2/N2 anneal. This suggests that the filling of O-vacancies in HfO2 is not adequate by itself to explain the EWF shift.
Backside DSIMS data showing N displacement from the TiN to the HfO2/TiN interface and slightly into the HfO2 following the 450 °C 10% O2/N2 post-TiN anneal. The insets emphasize that the HfO2/TiN interfacial edge, defined by the O and Ti concentrations, overlaps for both samples, indicating that the difference in N concentration near that interface is indeed evidence of N displacement.
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