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The schematic concept of increasing the subband energy spacings in a “3-gate QPC” device. The schematic diagram of (a) a conventional QPC and its potential profile and (b) a 3-gate QPC and its potential profile. By adjusting the voltages on the QPC gate and the middle gate, the potential profile and the depth of the conducting channel can be controlled. (c) The SEM picture of a 3-gate QPC device.
The conductance through a 3-gate QPC as a function of QPC gate voltage at different middle gate voltages. The middle gate voltage was varied from 0.3 V to 0.95 V in the steps of 0.05 V (right to left). All the measurements were performed at 4.2 K.
The differential conductance traces ) were measured for various fixed source-drain voltages . (a) The grey-scale plot of the transconductance traces obtained by numerical differentiation of the measured data. The transconductance is higher for the lighter colors. (b) The conductance measured when the source-drain bias is set to 0 V. (c) The dependence of the first subband energy spacing () on the middle gate voltage for the devices with 100 nm (dashed line) and 50 nm (solid line) wide middle gate.
The conductance quantization measured for a QPC with a 5 μm long channel length. The inset is the SEM picture of the device.
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