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Low-κ organic layer as a top gate dielectric for graphene field effect transistors
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10.1063/1.4711776
/content/aip/journal/apl/100/19/10.1063/1.4711776
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/19/10.1063/1.4711776
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Figures

Image of FIG. 1.
FIG. 1.

(a) Schematic diagram of the device structure. (b) Optical image of the actual device used in this study.

Image of FIG. 2.
FIG. 2.

(a) AFM of selectively deposited parylene C on exfoliated graphene. (b) TEM image showing parylene C and nickel electrode on exfoliated graphene.

Image of FIG. 3.
FIG. 3.

(a) Raman spectra of exfoliated graphene before (black line) and after (redline) parylene deposition. (b) Resistance as a function of back-gate voltage (VBG). The black lines indicate sweeps without parylene and the red lines are sweeps with parylene

Image of FIG. 4.
FIG. 4.

(a) Resistance as a function of top-gate voltage (VTG) with TG hysteresis of ∼0.02 V. (b) Measured total resistance RTOTAL (symbols) and simulated resistance (solid lines) vs. VTG-VDIRAC at the selected VBG biases.

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/content/aip/journal/apl/100/19/10.1063/1.4711776
2012-05-11
2014-04-21
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Low-κ organic layer as a top gate dielectric for graphene field effect transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/19/10.1063/1.4711776
10.1063/1.4711776
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