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Electron detrapping in thin hafnium silicate and nitrided hafnium silicate gate dielectric stacks
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View: Figures


Image of FIG. 1.
FIG. 1.

(a) Capacitance voltage (C–V) characteristics of nMOS capacitors with HfSi x O y and HfSiON gate stacks recorded before and after CVS at 2.5 V for 1000 s at room temperature. Symbols are from measurements and curves are from QM simulation. (b) C–V plot of HfSiON capacitor in the following sequence: fresh (dashed line), immediately after CVS at 2.5 V for 1000 s (solid line), and after zero-field relaxation for τr  = 1 h (dotted line) and 10 h (dashed-dotted line) followed by CVS. Inset: C–V characteristics of an nMOS capacitor with HfSi x O y gate stack measured in the following sequence: virgin (dashed line), immediately after CVS at 2.5 V (solid line) and −2.0 V (dotted line) followed by PBS.

Image of FIG. 2.
FIG. 2.

(a) Flat band voltage shift at room temperature due to self detrapping of trapped electrons in the high-κ layer as a function of logarithmic relaxation time τr . Electrons got trapped during CVS at room temperature. Zero-field relaxation results are shown after positive bias stress at various values of in several identical devices. (b) Number of detrapped electrons at room temperature as a function of detrapping time. Symbols are estimated from QM simulation of the measured C–V data. Curves are from logarithmic fits. (c) Plot of the slope b of the zero-field detrapping rate as a function of initial density NT of trapped electrons in high-κ layers. Symbols are estimated using the logarithmic fits to vs. τr data at room temperature as shown in (b). Curves are from linear regressions.

Image of FIG. 3.
FIG. 3.

(a) Variation of the density of electrons trapped after PBS at 2.5 V for 1000 s as a function of time during negative bias stress in two detrapping cycles. Each sequence comprising of the two repetitive stressing-detrapping cycles was measured on separate capacitors. Symbols are estimated from QM simulation of the measured C–V data using Eq. (1). Curves are fits to the data with the first-order exponential decay equation. (b) Evolution of negative oxide charge buildup with stress time in HfSiON capacitors under CVS at +2.5 V and −2.0 V. Inset: Stress time dependence of midgap voltage shift ΔV mg relative to the as-grown HfSiON device during negative bias CVS with as a parameter.

Image of FIG. 4.
FIG. 4.

Schematic energy band diagram showing the location of the electron traps in the high-κ layer and field induced tunnel detrapping depending on the strength of the negative gate bias.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Electron detrapping in thin hafnium silicate and nitrided hafnium silicate gate dielectric stacks