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(Color online) (a) Top: schematic layout of the PEO-gated surface-conductive diamond transistor. Drain and source contact are passivated with SU8 (light green) and silicone glue (red). The solid PEO (light pink) rests directly on the diamond surface and is contacted with the gate electrode. The conductivity of the p-type conductive channel in the diamond can be modulated by applying a gate voltage across the PEO/diamond interface. Bottom: Image of a 4 × 4 transistor array with common source and individual drain contacts. The transistor dimensions are 20 × 40 μm2. (b) Top: phase Φ and absolute impedance value |Z| of the diamond/PEO interface versus frequency taken at a gate voltage of 0.3 V; bottom: cyclic voltammetry of the diamond/PEO interface recorded at 10 mV/s.
(Color online) (a) Drain-source current (I DS ) versus drain-source voltage (U DS ) at different gate potentials showing transistor-typical behaviour with linear and saturation regions. (b) Sheet conductance in the linear region. The slope above the threshold voltage is 0.1 μS mV−1.
(Color online) (a) Sheet carrier (hole) concentration versus gate voltage as derived from Hall effect measurements for an electronic grade sample with an electrolyte gate configuration as well as a PEO gate configuration. (b) Corresponding Hall mobility as calculated from the sheet conductivity and carrier concentration.
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