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Stress time dependence of area density of interface states generated during PBTS (a) at room temperature with as a parameter and (b) at a given with stress temperature as a parameter. Symbols are from measurements and curves are from power-law fits.
Time evolution of during PBS (1000 s) and recovery (1000 s) cycles at two different temperatures. Solid and dashed curves are fits to and , respectively.
Stress time dependence of area density of interface states generated during PBTS at = 3.0 V at room temperature in TaN/SiO2/p-Si MOS capacitor having oxide thickness = 2.65 nm. Symbols are from measurement data, and curve is from power-law fit. Inset shows the variation of midgap voltage shift as a function of stress time during PBTS.
(a) Arrhenius plot of the PBTS induced interface states in HfSiON nMOS capacitors stressed at = 2.3 V for different times. (b) Variation of the maximum depletion capacitance relative to its as-fabricated value (left axis) and the fraction of passivated dopants in n-well (right axis) with stress time during PBTS at room temperature with stress voltage as a parameter. Lines are guides to the eye.
Arrhenius plot of the SILC densities () with sense voltage () as a parameter in HfSiON and HfSixOy nMOS capacitors stressed at = 2.3 V for 100 s. Both devices had a 1.0 nm thick interfacial SiO2 and a 2.5 nm thick high- layer.
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