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Vertically integrated submicron amorphous-In2Ga2ZnO7 thin film transistor using a low temperature process
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10.1063/1.4717621
/content/aip/journal/apl/100/20/10.1063/1.4717621
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/20/10.1063/1.4717621
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) The plan-view optical microscopy and (b) vertical scanning electron microscopy images of the fabricated V-TFT. The approximate channel length was 310 nm.

Image of FIG. 2.
FIG. 2.

(a) The IDS-VGS characteristics of the a-IGZO V-TFTs for various VDS and (b) sub-threshold slope at VGS of 0 V and Ioff as a function of VDS, where Ioff is defined IDS at VGS of −10 V.

Image of FIG. 3.
FIG. 3.

TCAD simulation results of thetransfer characteristics considering the different drain electrode length (5–600 nm), where the defects densities in (a) is assumed to be larger than that of (b) by one order of magnitude. Detailed defect densities are marked in the figures.

Image of FIG. 4.
FIG. 4.

(a) Sub-threshold slope and Ion current as a function of VDS, where Ion is defined IDS at VGS of 10 V. IDS-VGS characteristics for various VDS in (b) forward bias direction and (c) reverse bias direction.

Image of FIG. 5.
FIG. 5.

IDS as a function of VDS for various VGS in (a) forward bias direction and (b) reverse bias direction.

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/content/aip/journal/apl/100/20/10.1063/1.4717621
2012-05-17
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Vertically integrated submicron amorphous-In2Ga2ZnO7 thin film transistor using a low temperature process
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/20/10.1063/1.4717621
10.1063/1.4717621
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