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Threshold voltage shift and drain current degradation by negative bias temperature instability in Si (110) p-channel metal-oxide-semiconductor field-effect transistor
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10.1063/1.4722796
/content/aip/journal/apl/100/21/10.1063/1.4722796
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/21/10.1063/1.4722796
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) I ch-V g characteristics in (100) and (110) pMOSFETs. (b) C-V g characteristics in inversion region measured by split C-V g measurement. (c) Stress time dependence of ΔV th at different temperatures in (100) and (110) pMOSFETs.

Image of FIG. 2.
FIG. 2.

(a) Temperature and (b) stress field dependence of ΔV th in (100) and (110) pMOSFETs after the stress time of 4096 s.

Image of FIG. 3.
FIG. 3.

(a) Stress time dependence of ΔI cp in (100) and (110) pMOSFETs under the different stress voltages. (b) ΔQ it dependence of ΔV th in (100) and (110) pMOSFETs under the various stress conditions.

Image of FIG. 4.
FIG. 4.

(a) Stress time dependence of I ch under the various stress conditions. I ch is normalized by initial I ch. (b) ΔV th dependence of the normalized I ch under the various stress conditions.

Image of FIG. 5.
FIG. 5.

Normalized mobility plotted against inversion carrier density after the generation of interface traps by FN tunneling injection.

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/content/aip/journal/apl/100/21/10.1063/1.4722796
2012-05-23
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Threshold voltage shift and drain current degradation by negative bias temperature instability in Si (110) p-channel metal-oxide-semiconductor field-effect transistor
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/21/10.1063/1.4722796
10.1063/1.4722796
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