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ID-VG characteristics of a-IGZO TFTs before and after (a) DBIS and (b) G-DBIS. (c) CCH-VG transfer characteristics of the a-IGZO TFT before and after the DBIS and G-DBIS. The insert shows the CCH-VG curves as a function of applied stress time during DBIS.
The (a) CGS-VG and (b) CGD-VG transfer characteristics of the a-IGZO TFT before and after the DBIS and G-DBIS. (c) The CGD-VG transfer curves of the a-IGZO TFT after the drain bias stress with different gate biases.
Schematic diagram of hole-trapping mechanism in (a) the first stage and (b) the second stage of the DBIS. (c) Schematic diagram of electron-trapping mechanism after the G-DBIS.
The non-uniform hole-trapping model of electrical properties of CGD-VG curves obtained from device simulation.
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