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(a) Results of a step-stress experiment carried out as described in Ref. 3 with source floating, increasing voltages are applied between drain and gate for 120 s. Leakage current does not significantly increase as a consequence of stress, indicating that the “critical voltage” for reverse-bias degradation is greater than 100 V. (b) Power dissipation and channel temperature levels for the different stress conditions adopted within this work (drain voltage is 30 V). (c) False-color EL pattern measured in on-state conditions on one of the analyzed samples.
(a) Output characteristics (measured at increasing gate voltage levels, from −6 V to 0 V, step 1 V) and (b) transconductance curves (measured at increasing drain voltage levels, from 1 V to 3 V) before and after a 14 h stress test at VGS = −1 V, VDS = 30 V.
(a) EL vs gate voltage curves measured on one of the analyzed samples submitted to stress at VDS = 30 V, VGS = −1 V. (b) Decrease in drain current and (c) in the EL/ID signal measured on the same sample during stress.
(a) Degradation of drain current measured on identical devices submitted to stress at several gate voltage levels, with a drain voltage of 30 V. (b) Dependence of the EL signal and (c) of the degradation rate (percentage drain current decrease after 14 h of stress) on the gate voltage level used for the stress tests.
Dependence of TTF on the EL signal emitted by the devices during stress. Dashed line is a linear fit of the experimental data.
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