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Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications
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10.1063/1.4729930
/content/aip/journal/apl/100/25/10.1063/1.4729930
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/25/10.1063/1.4729930
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Figures

Image of FIG. 1.
FIG. 1.

Fabrication, experimental measurement, and simulation results for flexible p +-i-n + SiNW TFET on plastic substrates. (a) Schematic representation of the single-crystal p +-i-n + SiNWs derived from a bulk p-type (100) Si wafer using a fully CMOS-compatible top-down route. Note that the crystalline connections to the supporting posts at the end of the SiNWs are not shown to provide clarity. (b) and (c) SEM image of the crystallographic wet-etched Si wire (b), with the corresponding SiNW after size reduction oxidation of the Si wire and the subsequent nitride strip (c). In (c), chemical staining was performed after deposition of 150-nm-thick polycrystalline silicon in order to distinguish the clear SiNW from the surrounding oxide layer. (d) SEM image of the p +-i-n + SiNW after wet-chemical etching in order to verify spatially selective doping in designed p +-i-n + structure. (e) Optical microscope image of the flexible SiNW TFET on a plastic substrate and its schematic illustration. (f) Measured I ds-V gs transfer curves of the SiNW TFET. (g) Simulated device structure and the energy band diagram along the channel for the device in the ambipolar state (V gs = −3 V and V ds = 1 V), together with the corresponding BTBT generation rate.

Image of FIG. 2.
FIG. 2.

Suppression of ambipolar conduction in SiNW TFET. (a) and (b) Simulated device structures of device A (asymmetric doping between source and drain) and device B (gate-to-drain underlap) and the corresponding energy band diagrams along the channel for the devices in the ambipolar state (V gs = −3 V and V ds = 1 V), together with the corresponding BTBT generation rates. (c) and (d) Corresponding experimental I ds-V gs transfer curves showing the complete suppression of the ambipolar conduction with a negative gate bias.

Image of FIG. 3.
FIG. 3.

Electrical characteristics of multiple SiNW n- and p-TFET constituting flexible c-TFET inverter on plastic substrates. (a) Optical image of the flexible SiNW c-TFET inverter on a plastic substrate and its circuit diagram. (b) I ds-V gs plots of the multiple SiNW n- and p-TFET. The gate leakage of the devices is much lower than the I on current, and hence, the I on current can be considered to consist entirely of the BTBT current. (c) I ds-V ds plots of the devices. Almost perfect saturation of the drain currents is observed in the high V ds region because of the absence (depletion) of channel accumulation charge.

Image of FIG. 4.
FIG. 4.

Static characteristics of flexible c-TFET inverter on plastic substrates and its mechanical properties. (a) Static VTC in butterfly shape of the flexible SiNW c-TFET inverter on a plastic substrate for different V dd values. (b) and (c) Corresponding voltage gain characteristics and the power supply currents, respectively, as a function of input voltage. (d) Graphical determination of the VTC of the inverter for V dd = 3 V. The intersections of I dd-V out curves at various V in reflect the actual operating points of the VTC. (e) and (f) Mechanical properties of the inverter. For the surface strain values of up to 0.67%, only small changes in voltage gain and standby power are observed. In addition, the inverter has good fatigue properties even after bending cycles up to 2000 times under the applied tensile strain of 0.67%.

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/content/aip/journal/apl/100/25/10.1063/1.4729930
2012-06-21
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/25/10.1063/1.4729930
10.1063/1.4729930
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