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Model of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxide-semiconductor field-effect transistors
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10.1063/1.3678023
/content/aip/journal/apl/100/3/10.1063/1.3678023
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/3/10.1063/1.3678023
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(Color online) Simultaneously measured gate and body currents (I G and I B) in the two devices showing the RTN in the (a) [device 1] GIDL current and (b) [device 2] gate ET current under GIDL bias condition of V GS = −0.3 V and V DS = 1.5 V.

Image of FIG. 2.
FIG. 2.

(Color online) A schematic cross sectional view showing three different traps located in the gate dielectric on the drain overlapped by the gate along the width direction. Case 1 shows that a trap is located in the gate dielectric, and no defect is located in several Debye lengths from the trap. Case 2 shows that a trap is located at a position near an I ET percolation path through the dielectric. Case 3 shows that a trap is located inside the gate dielectric on an I GIDL percolation path (a localized defect region at the surface of the drain).

Image of FIG. 3.
FIG. 3.

(Color online) (a) Extracted amplitude (ΔI B) and relative amplitude (ΔI B/I B) of the RTN versus vertical trap position (x T) in measured devices showing the RTN in the GIDL current when V GS = −0.3 V and V DS = 1.5 V. (b) Extracted ΔI B versus the distance (D t) between the center of a GIDL percolation path and a trap position as a parameter of x T in the simulation results.

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/content/aip/journal/apl/100/3/10.1063/1.3678023
2012-01-18
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Model of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxide-semiconductor field-effect transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/3/10.1063/1.3678023
10.1063/1.3678023
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