Full text loading...
(Color online) Summary of one of the step-stress experiments carried out within this work. During stress at moderate gate voltage levels (here, for |VG| < 30 V), gate current decreases monotonically during each step. At a certain step (here, for VG = −30 V), gate current becomes noisy, indicating that the device is about to degrade. Degradation is detected as a non-recoverable increase in gate current (see step at VG = −35 V and beyond). Inset: schematic representation of the adopted stress conditions.
(Color online) Results of a constant-voltage reverse-bias stress test. The three graphs report the variation of (a) gate current, (b) amplitude of the noise on gate current, and (c) threshold voltage during stress time.
(Color online) Results of the time-resolved EL measurements carried out during stress at VG = −30 V, VD = VS = 0 V (same sample as in Figure 2). The figure on the top represents a schematic micrograph of one of the analyzed samples. Frames below are false-color images reporting the distribution of EL for increasing stress times.
(Color online) (a) EL spectra measured under reverse-bias conditions on one of the analyzed HEMTs (spectra were collected at several gate voltage levels, with VD = VS = 0 V). (b) A schematic explanation of the reverse-bias EL process.
(Color online) (a) Schematic representation of the model used to explain the recoverable modifications in gate leakage current and threshold voltage. (b) Dependence of tBD on the initial leakage current, for devices with different initial leakage current levels aged at VG = −30 V, VD = VS = 0 V.
Article metrics loading...