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Effect of channel widths on negative shift of threshold voltage, including stress-induced hump phenomenon in InGaZnO thin-film transistors under high-gate and drain bias stress
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10.1063/1.3679109
/content/aip/journal/apl/100/4/10.1063/1.3679109
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/4/10.1063/1.3679109
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Figures

Image of FIG. 1.
FIG. 1.

(Color online) Transfer characteristics of IGZO TFTs with (a) channel width = 10 μm, (b) channel width = 50 μm, and (c) channel width = 500 μm before and after VGS = VDS = 12 V at 30 °C for 5000 s, measured at VDS = 10 V (channel length = 22 μm).

Image of FIG. 2.
FIG. 2.

(Color online) (a) Schematic diagram of degradation in the inverted staggered IGZO TFTs, normalized value of (b) gate-to-drain capacitance (CGD) and (c) gate-to-source capacitance (CGS) of the IGZO TFTs before and after high gate and drain bias stress (VGS = VDS = 12 V for 5000 s), measured at 1 MHz (channel width/length = 500/22 μm).

Image of FIG. 3.
FIG. 3.

(Color online) Transfer characteristics of IGZO TFTs with (a) channel width = 32 μm (single channel), and (b) width = (8 μm) × 4 (4-channel) under VGS = VDS = 12 V at 30 °C for 5000 s, measured at VDS = 10 V (channel length = 6 μm).

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/content/aip/journal/apl/100/4/10.1063/1.3679109
2012-01-23
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Effect of channel widths on negative shift of threshold voltage, including stress-induced hump phenomenon in InGaZnO thin-film transistors under high-gate and drain bias stress
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/4/10.1063/1.3679109
10.1063/1.3679109
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