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(Color online) (a) Top view of the pi-gate TANOS NVM. Bit-S and bit-D are defined for 2-bit operation. (b) Cross-sectional TEM images of this NVM device from A-A’ direction. The thickness of the layers is marked in inset image. (c) Endurance and (d) retention characteristics at 85 °C of the pi-gate TANOS NVM.
(Color online) (a) Effect of drain voltage on tunneling speed. (b) Simulation of vertical electric field in tunneling oxide and tunneling current density.
(Color online) (a) CHEI programming and BTBT-HHI erasing (b) MFN programming and erasing. (c) Energy band diagram of the TANOS NVM under F-N programming and erasing.
(Color online) (a) and (b) Transfer curves of the NVM devices used in one-bit programming by two 2-bit operations; (c) and (d) are the curves of such devices in one-bit erasing.
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