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(Color online) (a) Device voltage waveform at the set pulse voltage of 0.9 V and the set pulse width of 1 μs and low-field resistance at various set pulse widths. (b) Changes in low-field resistance with the increase of set overwrite up to 100 counts (repetition period = 60 s) at two pre-threshold and two post-threshold set pulse widths. The (a) and (b) are from TiN 100 nm/Ge1Sb2Te4 100 nm/TiN 100 nm layered structures with 90 nm contact size.
Device voltage waveforms superimposed by time-resolved low-field resistances at the set voltages of (a) 0.76 V, (b) 0.8 V, (c) 0.9 V, (d) 1.0 V, (e) 1.2 V, (f) 1.4 V, (g) 1.6 V, and (h) 1.8 V. The device was always reset with 2.0 V and 100 ns pulse (20 mW) before each set operation for consistency.
Set power dependencies of (a) total set time tset , (b) the incubation time tinc , and (c) the growth time tgro in the current-induced crystallization process.
(Color online) Schematic temperature profiles increased by electrical set pulse various powers and T-T-T diagram of Ge-Sb-Te material.
(Color online) Resistance changes in the cells with Ge2Sb2Te5 100 nm on TiN electrode with 45 nm contact size as a function of set pulse width in three different pulse forms, inserted on the top of Fig. 5. When the pulse width is varied, the durations of high-power and low-power are always the same in case of two-step pulse while the falling width is only changed in case of slow-quenched pulse, respectively. If otherwise, the rising and falling widths are fixed to be 10 ns. The significantly lower power scale than those of Fig. 3 is attributed to the well-designed cell structure for maximizing Joule heating efficiency in the phase change memory device with 45 nm technology.
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