1887
banner image
No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Fabrication of high-performance fully depleted silicon-on-insulator based dual-gate ion-sensitive field-effect transistor beyond the Nernstian limit
Rent:
Rent this article for
USD
10.1063/1.3685497
/content/aip/journal/apl/100/7/10.1063/1.3685497
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/7/10.1063/1.3685497

Figures

Image of FIG. 1.
FIG. 1.

(a) A cross-sectional FEI 430 SEM micrograph of SOI substrate. The thicknesses of top Si and BOX layer are 107 nm and 224 nm, respectively. (b) A cross-sectional TEM image of the SiO2 sensing membrane. TEM analysis was conducted on a JEOL JEM-3010 TEM operating at 300 kV. The thickness of SiO2 sensing membrane grown by dry oxidation is 28.2 nm.

Image of FIG. 2.
FIG. 2.

(Color online) (a) ID-VG and (b) ID-VD electrical characteristics of a SOI DG MOSFET with SiO2 sensing membranes measured by top gate or back gate operations. The channel length and width are 10 μm and 10 μm, respectively.

Image of FIG. 3.
FIG. 3.

(Color online) Transfer curves of (a) SG and (b) DG ISFET for different pH buffer solutions. The drain bias is set at 1 V. The responsive voltage of the sensor for each pH buffer solution shown in the insets of figure was defined as the corresponding gate voltages to the drain current (Reference current: IR) of 1 μA and 100 nA for SG and DG ISFETs, respectively.

Image of FIG. 4.
FIG. 4.

(Color online) (a) Hysteresis phenomenon for three buffer solutions measured by SG and DG sweep modes. The ISFETs were subjected to the pH loop of 7-10-7-4-7 for 60 min. The inset shows the hysteresis widths of each responsive voltage for pH 4, pH 7, and pH 10 buffer solution. (b) Drift characteristics by the SG and DG measurements in pH 7 buffer solution for 12 h.

Tables

Generic image for table
Table I.

Electrical characteristics of the SOI-MOSFET for top gate and back gate mode operations.

Generic image for table
Table II.

Sensing properties of the SOI-ISFETs obtained from top gate and back gate measurements.

Loading

Article metrics loading...

/content/aip/journal/apl/100/7/10.1063/1.3685497
2012-02-14
2014-04-18
Loading

Full text loading...

This is a required field
Please enter a valid email address
752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Fabrication of high-performance fully depleted silicon-on-insulator based dual-gate ion-sensitive field-effect transistor beyond the Nernstian limit
http://aip.metastore.ingenta.com/content/aip/journal/apl/100/7/10.1063/1.3685497
10.1063/1.3685497
SEARCH_EXPAND_ITEM