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Tunable aluminium-gated single electron transistor on a doped silicon-on-insulator etched nanowire
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10.1063/1.4750251
/content/aip/journal/apl/101/10/10.1063/1.4750251
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/10/10.1063/1.4750251
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Device structure and characterization. (a) Schematic cross section of the device indicating the accumulation of a 2DEG at the interface and the local depletion by the barrier gates. (b) Scanning electron microscopy top-view of the device before the top gate is deposited. (c) Turn-on characteristics of the device at 300 K and 290 mK when a positive voltage is applied to all the three surface gates. . (d) Data from a different device at 4.2 K. Drain barrier gate presents an electrical discontinuity. Dual-side gating (DB1 and DB2 simultaneously biased) allows flexible control of the tunnel barrier.

Image of FIG. 2.
FIG. 2.

SET characterization at 290 mK. (a) Device conductance as a function of the barrier gate voltages for and . (b) Coulomb blockade diamonds as a function of for and . Differential conductance measured using a lock-in excitation voltage of .

Image of FIG. 3.
FIG. 3.

Device tunability. (a) Stability diagram for a large range of top gate voltages showing periodic regular Coulomb diamonds. Lock-in AC excitation of . and . (b) Total capacitance of the SET island as a function of . Periodic CB oscillations for different barrier gates biasing conditions for : (c) , (d) , (e) .

Image of FIG. 4.
FIG. 4.

Dopant signatures. (a) Source barrier voltage differential conductance at low . Two clear transition a, b are observable in the subthreshold regime as well as irregular resonances c at larger . (b) Source barrier stability diagram acquired with a lock-in AC excitation voltage of . The charging energy of the system is 20 meV.

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/content/aip/journal/apl/101/10/10.1063/1.4750251
2012-09-05
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Tunable aluminium-gated single electron transistor on a doped silicon-on-insulator etched nanowire
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/10/10.1063/1.4750251
10.1063/1.4750251
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