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Role of measurement voltage on hysteresis loop shape in Piezoresponse Force Microscopy
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View: Figures


Image of FIG. 1.
FIG. 1.

(a) Voltage waveform applied to the tip: overall (top) and zoomed-up area (bottom). Field on and off measuring states are shown. (b) Schematics of nanoscale capacitor and measurement setup. (c) Topographic map of capacitor sample with location of one of the 180-by-180 nm measurement regions highlighted in red, (d) Piezoresponse (PR) hysteresis loops averaged over a 3 × 3 (180 × 180 nm2) grid. Shown are loops measured in the on and off states at 0.25 V and 4 V driving biases.

Image of FIG. 2.
FIG. 2.

Evolution of piezoresponse hysteresis loops in nanocapacitors with increasing AC driving voltage for (a) field-off and (b) field-on states. Bias dependence of the effective hysteresis loop parameters for field-off (c) and field-on (d) loops.

Image of FIG. 3.
FIG. 3.

Normalized piezoresponse hysteresis loop averaged over 10 × 10 (1.5 × 1.5 μm2) grid for PZT thin film. Shown are (a) field-off and (b) field-on loops for different driving biases and (c), (d) loop height and width vs. driving bias.

Image of FIG. 4.
FIG. 4.

BiFeO3 sample: Piezoresponse loops for field-off (a) and -on (b) states recorded on a 10 × 10 (2 × 2 μm) grid, (c) typical topography of the sample, and (d) in-plane domain structure.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Role of measurement voltage on hysteresis loop shape in Piezoresponse Force Microscopy