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High-mobility p-channel metal-oxide-semiconductor field-effect transistors on Ge-on-insulator structures formed by lateral liquid-phase epitaxy
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10.1063/1.4766917
/content/aip/journal/apl/101/20/10.1063/1.4766917
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/20/10.1063/1.4766917

Figures

Image of FIG. 1.
FIG. 1.

Observation of the Ge wire fabricated by LLPE with RTA at 1035 °C for 1 min. (a) Schematic illustration of LLPE growth from the Si seed regions, (b) typical optical microscope image, (c) top-view SEM image, (d) EDX mapping of Ge element, and (e) EBSD image of a Ge wire. The SEM, EDX, and EBSD observations were carried out after the SiO2 capping layer was removed by wet etching.

Image of FIG. 2.
FIG. 2.

Micro-probe Raman spectra obtained from the middle portions of the Ge wires formed by LLPE with RTA (a) at 1035 °C for 1 min and (b) at 950 °C for 1 s. The dotted lines in the figures correspond to a reference spectrum taken from the Ge(100) bulk substrate. Raman signals around 293 cm−1 and 390 cm−1 correspond to Ge-Ge and Si-Ge vibration modes, respectively.

Image of FIG. 3.
FIG. 3.

Summary of Raman spectroscopy measurements. (a) Si distribution in the LLPE-grown Ge wires formed by RTA at 950 °C for 1 s or 1035 °C for 1 min. (b) Strain analysis of the Ge wire formed at 950 °C.

Image of FIG. 4.
FIG. 4.

ID-VG characteristics of back-gate GOI MOSFETs fabricated under various conditions. The Ge-channels were formed by LLPE (a) at 950 °C for1 s and (b) 1035 °C for 1 min and (c) by SPE at 600 °C for 2 h. The as-deposited amorphous Ge-channel (d) does not exhibit switching behavior. The gate width and length of these devices were identical (W/L: 3.8/29.3 μm), except for the device annealed at 950 °C for 1 s (W/L: 4.0/35.1 μm).

Image of FIG. 5.
FIG. 5.

Performance of the back-gate GOI MOSFET with the LLPE-grown Ge wire. (a) ID-VD characteristics at gate bias ranging from −10 to −30 V in −5 V step; (b) ID-VG characteristics at drain bias ranging from −50 to −200 mV in −50 mV step. The inset is a schematic of the back-gate transistor.

Tables

Generic image for table
Table I.

Hole mobilities extracted from back-gate GOI and SOI devices. The reported value for the back-gate GOI device fabricated by Ge condensation19 is also shown.

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/content/aip/journal/apl/101/20/10.1063/1.4766917
2012-11-13
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: High-mobility p-channel metal-oxide-semiconductor field-effect transistors on Ge-on-insulator structures formed by lateral liquid-phase epitaxy
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/20/10.1063/1.4766917
10.1063/1.4766917
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