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The schematic diagram of gated diode π-region surface condition at (a) accumulation, (b) depletion, and (c) inversion situation.
(a) Electrical performance comparison between UPD and UGD with different SiO2 passivation layer thickness. (b) Electrical performance comparison between UPD and GD at saturated gate bias. (c) Correlation between gate bias and SiO2 passivation layer thickness.
The correlation between the reverse dark current density and gate bias of sample C at different diode operation bias.
(a) The peak responsivity (at 9.9 μm) and (b) QE at peak responsivity at different diode operation bias at 77 K.
Detectivity of UPDs, UGDs, and GDs at saturation gate bias calculated at different operation bias. The calculation of detectivity bases on the inset equation, with Ri is the responsivity, J is the dark current density, q is the charge of electron, kb is the Boltzmann constant, T is the temperature, and RA is the differential resistance-area product.
The differential-resistance-area product at −100 mV (RA−100 mV), saturated gate bias, and peak detectivity (D*) of UPD, UGD, and GD at saturation bias.
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