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(a) Optical microscope image of the graphene-on-silicon device before depositing the electrolyte top gate and (b) schematic diagram of the device structure.
I-V bias characteristics taken at different gate voltages (Vg) of (a) graphene-Si (p-type) and (b) graphene-Si (n-type) devices. The inset figures show the I-V characteristics at Vg = 0 V.
Low bias conductance plotted as a function of graphene Fermi energy for (a) graphene-Si (p-type) and (b) graphene-Si (n-type) devices. The right and left solid vertical lines represent the conduction and valence bands of silicon, and the middle dashed line represents the Fermi energy of silicon.
(a) Graphene-silicon I-V bias characteristics taken under illumination at different gate voltages. (b) Short circuit current (Isc ) with and without illumination plotted as a function of graphene Fermi energy.
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