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Low-power resistive switching in Au/NiO/Au nanowire arrays
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View: Figures


Image of FIG. 1.
FIG. 1.

(a) Sketch of the sample and experimental setup and (b) 0.5 × 0.5 μm2 topographic AFM image of the surface of the sample.

Image of FIG. 2.
FIG. 2.

Topography (a), line profile (inset) and current mapping (b) of formed NWs. (c) and (e) are 0.7 × 0.7 μm2 AFM images where the corrugation represents the topography of the surface while the colors are related to the acquired current map, respectively, before and after the forming sweep in (d). In (e),the dark spot in the center evidences the formed nanowire.

Image of FIG. 3.
FIG. 3.

Examples of current-voltage switching characteristics with subsequent reading stages: (a) forming, (b) reset, and (c) set operations. Empty squares represent the forward sweeps and empty circles the backward ones. (d) Evolution of the resistances measured in few switching cycles. The intermediate state is shaded in the graph. The inset shows the retention for the high resistance (squares) and the low resistance (circles) states.

Image of FIG. 4.
FIG. 4.

(a) Collection of literature data (see Refs. 56111314171820212829) for the reset current as a function of the LRS resistance and (b)memory element size of NiO-based devices for comparison with our results (filled balls). For comparison, the empty symbols indicate the reset currents for NW based memories (see Refs. 17, 18, 20, and 21).


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Low-power resistive switching in Au/NiO/Au nanowire arrays