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Charge loss mechanism of non-volatile V3Si nano-particles memory device
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Image of FIG. 1.
FIG. 1.

(a) Cross-sectional schematics and FE-TEM image, respectively, of the nano-floating gate flash memory with V3Si nano-particles embedded in the SiO2 dielectric layer. (b) XPS spectra of Si 2 p from the uppermost surface of silicide.

Image of FIG. 2.
FIG. 2.

(a) ID-VG characteristics at 35  °C after P/E operations by pulse voltages of ±8 V and ±9 V for 500 ms, respectively. (b) Threshold voltage shifts of the memory device as a function of the program(+)/erase(−) pulse time after applied P/E voltages of +9 V/−9 V, and (c) the charge retention property after P/E pulse voltages of +9 V/−9 V were applied for 1 s. The program, erase, and retention properties of the V3Si nano-particles memory device were measured at temperatures of 35, 50, 80, and 110  °C, respectively.

Image of FIG. 3.
FIG. 3.

Normalized charge loss characteristics of the V3Si nano-particles memory devices at temperatures of 35, 50, 80, and 110  °C. The inset is an Arrhenius plot of retention time and reciprocal temperature.

Image of FIG. 4.
FIG. 4.

The endurance property of the memory device at 20  °C after the P/E cycles at pulse voltages of +9 V/−9 V for 1 s.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Charge loss mechanism of non-volatile V3Si nano-particles memory device