Full text loading...
(a) Cross-sectional schematics and FE-TEM image, respectively, of the nano-floating gate flash memory with V3Si nano-particles embedded in the SiO2 dielectric layer. (b) XPS spectra of Si 2 p from the uppermost surface of silicide.
(a) ID-VG characteristics at 35 °C after P/E operations by pulse voltages of ±8 V and ±9 V for 500 ms, respectively. (b) Threshold voltage shifts of the memory device as a function of the program(+)/erase(−) pulse time after applied P/E voltages of +9 V/−9 V, and (c) the charge retention property after P/E pulse voltages of +9 V/−9 V were applied for 1 s. The program, erase, and retention properties of the V3Si nano-particles memory device were measured at temperatures of 35, 50, 80, and 110 °C, respectively.
Normalized charge loss characteristics of the V3Si nano-particles memory devices at temperatures of 35, 50, 80, and 110 °C. The inset is an Arrhenius plot of retention time and reciprocal temperature.
The endurance property of the memory device at 20 °C after the P/E cycles at pulse voltages of +9 V/−9 V for 1 s.
Article metrics loading...