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Temperature-dependent capacitance-voltage analysis of defects in Al2O3 gate dielectric stacks on GaN
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10.1063/1.4769827
/content/aip/journal/apl/101/24/10.1063/1.4769827
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/24/10.1063/1.4769827
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

TEM of ∼8 nm Al2O3/GaN gate stack under investigation in this work.

Image of FIG. 2.
FIG. 2.

Capacitance-voltage measurement of Pd/Al2O3/GaN MOS device at 77 K. The absence of frequency dispersion in accumulation suggests no border trap response in these devices. Inset: extracted parallel conductance versus gate voltage.

Image of FIG. 3.
FIG. 3.

Schematic representation of the effect of measuring the capacitance-voltage profiles at elevated temperatures. With increasing measurement temperature, the portion of the bandgap for which defect responses can be observed increases.

Image of FIG. 4.
FIG. 4.

Capacitance-voltage profiles measured at (a) 300 K and (b) 500 K. At 500 K, the defect response as a function of frequency is observed. Insets: Extracted parallel conductance versus gate voltage.

Image of FIG. 5.
FIG. 5.

(a) Measured capacitance-voltage profiles at 800 kHz from 77 K to 500 K for the Pd/Al2O3/GaN structure. At 500 K, there is a stretch out of the profile and an increase in Cmin. The stretch out and increased Cmin at higher temperature can be attributed in part to the shift in the equilibrium bulk Fermi level with respect to the band edge in these highly doped samples. (b) Simulated capacitance-voltage profiles at 300 K and at 500 K without and with the pyroelectric charge component as estimated from Ref. 24.

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/content/aip/journal/apl/101/24/10.1063/1.4769827
2012-12-12
2014-04-21
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Temperature-dependent capacitance-voltage analysis of defects in Al2O3 gate dielectric stacks on GaN
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/24/10.1063/1.4769827
10.1063/1.4769827
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