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Reduced electron back-injection in Al2O3/AlOx/Al2O3/graphene charge-trap memory devices
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10.1063/1.4770381
/content/aip/journal/apl/101/24/10.1063/1.4770381
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/24/10.1063/1.4770381
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Figures

Image of FIG. 1.
FIG. 1.

Fabrication procedures of AXA-gFET CTFM. (a) Transfer of SLG onto the SiO2/Si substrate. The right-hand-side graph displays the Raman spectrum of SLG on SiO2/Si. (b) Defining the channel area using photolithography. (c) Formation of source/drain electrode by Ti/Al evaporation. The right-hand-side photograph shows the scanning electron microscopy image of the channel area. (d) Deposition of tunnel oxide Al2O3 (∼15 nm) by ALD and subsequent oxygen ion bombardment to form the AlOx charge storage layer. (e) Deposition of control oxide Al2O3 (∼25 nm) by ALD and formation of gate electrode using ITO evaporation. The right-hand-side graph represents a typical V-shaped ID-VG curve of the AXA-gFET.

Image of FIG. 2.
FIG. 2.

Program and erase operation of AXA-gFETs composed of AlOx charge storage layers formed by oxygen ion bombardment under (a) POIB = 100 W and (b) POIB = 200 W. Samples were programmed using a voltage stress of VP = 24 V for 10 ms and erased by VE = −22 mV for 30 ms.

Image of FIG. 3.
FIG. 3.

(a) ΔVDirac as a function of |VP/E| for AXA-gFETs composed of AlOx charge storage layers formed by the oxygen ion bombardment under POIB = 100 (AXA-100) and 200 W (AXA-200). The pulse times for programming and erasing were 10 ms and 30 ms, respectively. The inset represents the reduced electron back injection at negative gate bias due to a thicker triangular potential barrier at the control oxide region. (b) Retention characteristics of AXA-100 and AXA-200. Samples were programmed by using a voltage stress of VP = 21 V for 10 ms and erased by VE = −23 mV for 30 ms.

Image of FIG. 4.
FIG. 4.

Potential profiles of the materials composed in AXA-gFET (a) before and (b) after contact. Energy band diagrams of (c) AXA-gFET and (d) AHA-gFET under negative gate bias (VG = −V1). The equivalent circuits illustrated at the bottom of (c) and (d) correspond to the series capacitance of AXA in (c) and AHA in (d), respectively.

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/content/aip/journal/apl/101/24/10.1063/1.4770381
2012-12-11
2014-04-25
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Reduced electron back-injection in Al2O3/AlOx/Al2O3/graphene charge-trap memory devices
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/24/10.1063/1.4770381
10.1063/1.4770381
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