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Seeding atomic layer deposition of high-k dielectric on graphene with ultrathin poly(4-vinylphenol) layer for enhanced device performance and reliability
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10.1063/1.4737645
/content/aip/journal/apl/101/3/10.1063/1.4737645
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/3/10.1063/1.4737645
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Figures

Image of FIG. 1.
FIG. 1.

Surface morphology of (a) bare CVD graphene, (b) Al2O3/graphene, (c) functionalized graphene, and (d) Al2O3/functionalized graphene films. Scan size is 1 × 1 μm2 for all images. The rms surface rougness of graphene becomes much smoother after the functionalization using PVP. The Al2O3 film deposited on the functionalized CVD graphene shows a much smoother morphology than that of the Al2O3 on bare CVD graphene.

Image of FIG. 2.
FIG. 2.

(a) AT-FTIR spectroscopy of the functionalized CVD graphene surface with PVP, showing the presence of O-H and C-H functional groups. (b) Raman spectroscopy of the monolayer CVD graphene before and after functionalization with PVP. The measurement is performed with an excitation wavelength of 514 nm. The PVP was uniformly formed while preserving the sp2 carbon framework of the large-scale graphene.

Image of FIG. 3.
FIG. 3.

(a) Schematic diagram showing top-gate graphene FET structure with PVP-seeded Al2O3 gate dielectric. (b) Microscopy images showing large scale device integration. (c) Representative ID-VG characteristics of top-gate graphene FET before and after the CVD graphene channel is functionalized with PVP. The channel length and width of the devices are 4 and 8 μm, respectively. The inset figure shows the transconductance of the graphene FETs with different gate dielectrics as a function of gate voltage. (d) Gm-VG characteristics of the PVP-seeded graphene FET for different drain voltages. The maximum peak transconductance is as high as 200 μS/μm at VDS  = 1 V.

Image of FIG. 4.
FIG. 4.

The time-dependent behavior of VDirac and the carrier mobility of the graphene FETs (a) before and (b) after the functionalization of graphene channel region with PVP seeding layer. The gate stress field is 0.4 MV/cm. The PVP-seeded device has a much smaller ΔVDirac (0.7 V) than that of the control device (2 V). A negligible carrier mobility change after gate bias stress is obtained with the functionalized graphene channel layer.

Image of FIG. 5.
FIG. 5.

The time-dependent VDirac shift of graphene FETs with the two different dielectrics. The experimental results were well fitted to the stretched exponential function. Determination coefficients (R2) showing the quality of the fitting are close to unity. The device with PVP-seeded Al2O3 gate dielectric has a much smaller ΔVDirac (∞) (1.1 V) than that of the control device (2.7 V).

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/content/aip/journal/apl/101/3/10.1063/1.4737645
2012-07-18
2014-04-18
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Seeding atomic layer deposition of high-k dielectric on graphene with ultrathin poly(4-vinylphenol) layer for enhanced device performance and reliability
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/3/10.1063/1.4737645
10.1063/1.4737645
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