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A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology
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10.1063/1.4739937
/content/aip/journal/apl/101/5/10.1063/1.4739937
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/5/10.1063/1.4739937
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Simplified process flow: (a) Boron diffusion; (b) patterning the device layer and removing the exposed BOX layer; (c) Al deposition and patterning to form traces and pads; (d) 1st 3 μm parylene deposition; (e) patterning the parylene openings and etching away underneath metal traces; (f) XeF2 etching to release the devices; (g) 2nd 10 μm parylene deposition; (h) patterning the parylene layer and releasing the device.

Image of FIG. 2.
FIG. 2.

A bent flexible device held by a pair of tweezers.

Image of FIG. 3.
FIG. 3.

Optical micrograph of four MOSFETs with different channel widths.

Image of FIG. 4.
FIG. 4.

SEM image of a MOSFET integrated on the flexible substrate.

Image of FIG. 5.
FIG. 5.

Cross sectional SEM image of the flexible device.

Image of FIG. 6.
FIG. 6.

(a) I sd-V sd curves of one PMOS device with different V sg; (b) shift of I sd-V sd curves of one PMOS device when the device was deformed (V sg is fixed at 15 V).

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/content/aip/journal/apl/101/5/10.1063/1.4739937
2012-07-31
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/5/10.1063/1.4739937
10.1063/1.4739937
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