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(a) Optical image of the CNT transistor array on SiO2/Si and HfO2/Si substrates. Channel lengths are 3, 5, 7, and 9 μm, and channel widths are 10, 20, and 30 μm. (b) Schematic structure of bottom–gate CNT TFT using SiO2 100 nm and HfO2 30 nm dielectric layer. Transfer characteristics (Id-Vg) of CNT-TFT devices fabricated on (c) SiO2/Si and (d) HfO2/Si substrates under positive gate bias stress times. The magnitude of the gate bias was fixed at 2.5 MV/cm, and the source-drain bias was fixed at 1 V. All of the measurements were taken at room temperature under ambient conditions.
Threshold voltage shift (ΔVth) with stress time in CNT-TFTs at different gate biases (a) on a SiO2 gate insulator and (b) on a HfO2 gate insulator. (c) The gate bias strength range was varied from 1 MV/cm to 2.5 MV/cm. The solid symbols represent the experimental data, and the solid lines were fitted to experimental data using Eq. (1).
Transfer characteristics of CNT-TFTs (fabricated on different insulators) before and after relaxation by applying a different gate bias stress. Devices were fabricated on (a) SiO2 gate insulators or (b) HfO2 gate insulators. The devices recovered to the original state after stressing for 2000 s and were then exposed to air for 1000 s.
(a) The evolution of the threshold voltage shift (ΔVth) variation with respect to positive gate bias stress and recovery. A gate bias stress of 2.5 MV/cm for 2000 s was applied. (b) Schematic showing the electric-field induced adsorption of oxygen molecules on SiO2 gate insulators under PGBS. (c) Schematic showing the electric-field induced adsorption of water molecules on HfO2 gate insulators under PGBS.
The extracted parameters of threshold voltage shift (ΔVth), relaxation time (τ), and stretch exponential factor (β) for various dielectric layers. Stress time is fixed at 2000 s for all of the cases.
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