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Solution-assisted manufacturing of scaled carbon nanotube array transistors. (a)-(g) Schematic illustrations of the manufacturing steps for obtaining a planar device with embedded gate electrodes [labeled g in (e) and (g)] and deposition electrodes [labeled a in (e) and (f)]. In (g), source (s) and drain (d) electrodes of the transistor are also indicated. (h) Scanning electron microscope image of the dual channel device having a channel width of 2 × 20 μm. (Inset) Magnified and colorized scanning electron microscopy image of the transistor channel showing 3 parallel carbon nanotubes (highlighted by red arrows) bridging the gated region (gray color) between source and drain electrodes (golden color).
Electrical DC characteristics of the carbon nanotube array transistor. (a) Measured electrical Id -Vg transfer characteristics (black lines) and transconductance gm (red squares). (b) Measured electrical Id -Vd output characteristics (black lines) and output conductance gd (blue squares). The magnitude of the electrical parameters Vd , Vg in the respective voltage sweeps are indicated on top.
Electrical AC characteristics of the carbon nanotube array transistor. (a) The as-measured, extrinsic short-circuit current gain (h21 , red squares) shows −20 dB/decade roll-off (black line: 1/f-fit) and becomes 0 dB at the current gain cut-off frequency fT . The extrinsic, maximum available power gain (MAG, blue rings) and the extrinsic, unilateral power gain (U, green circles) becomes 0 dB at the maximum frequency of oscillation, fMAX . (b)Intrinsic short-circuit current gain (h21 , red squares; black line: 1/f-fit), intrinsic maximum available power gain (MAG, blue rings), and intrinsic unilateral power gain (U, green circles). The measurement was performed at Vd = −2 V and Vg = −2 V.
(a) Plot of the measured transconductance gm (red squares) as function of the experimental, intrinsic current gain cut-off frequency fT for four different carbon nanotube array transistors with gate length of . A linear fit (black line) delivers the experimental value of the gate capacitance that is also indicated. (b) Highest intrinsic cut-off frequency fT achieved (black circles) versus number of experimental iteration. The vertical lines separate the iteration steps that are based on different device (gate) concepts. In the device schematics, the gate electrodes are visualized in red color, source and drain electrodes are shown in blue color.
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