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Ultra high density three dimensional capacitors based on Si nanowires array grown on a metal layer
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Image of FIG. 1.
FIG. 1.

Integration flow to make nanowires capacitor in the interconnects. (a) A nanowire capacitor in the interconnects above the transistors in a microelectronic chip. (b) Main integration steps used in this study to make our nanowire devices compatible with interconnects: 1—Multilayer deposition stack composed of titanium silicide, titanium nitride, copper and silicon dioxide. 2—Photolithography and etching of the silicon dioxide to the copper. 3—Nanowire growth with copper as catalyst. 4—Optional nanowire cleaning followed by Alumina and titanium nitride deposition. 5—Photolithography and etching to define the contact pads. 6—C(V) and I(V) measurements are performed between the top metal contact and the substrate backside.

Image of FIG. 2.
FIG. 2.

SEM pictures of the nanowire devices. (a) SEM cross-section of the nanowires after their growth on titanium nitride and (inset) SEM top view of the complete device with the connecting pad on the left (the scale bar is 75 μm long). (b) SEM cross-section of a nanowire after alumina and titanium nitride depositions.

Image of FIG. 3.
FIG. 3.

TEM characterizations along a nanowire and on a nanowire slice after Al2O3 and TiN deposition on the nanowires. (a) 3D Tomography reconstruction using low-loss energy filtered TEM. (b) One slice from the reconstructed nanowire showing their hexagonal cross-section along their length. (c) and (d), EFTEM with bright contrast variation showing the oxygen (c) and titanium (d) maps. (e) High resolution TEM image of a real nanowire cross-section showing in the inset the alumina layer crystallinity. (f) and (g), oxygen (f) and titanium (g) maps.

Image of FIG. 4.
FIG. 4.

Capacitance-voltage measurements (symbols) and simulations (lines) on nanowire devices compared to the measured reference without nanowires. The measured curves have been obtained at ambient temperature and 1 kHz for devices with 10 nm (blue circles) and 20 nm (green rhombuses) of alumina. For comparison a reference without nanowires and 10 nm of alumina has been plotted (red triangles). The obtained simulated curves for 10 nm (blue line) and 20 nm (green line) of alumina have been plotted on the same graph.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Ultra high density three dimensional capacitors based on Si nanowires array grown on a metal layer