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Low-temperature pseudo-metal-oxide-semiconductor field-effect transistor measurements on bare silicon-on-insulator wafers
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10.1063/1.4748984
/content/aip/journal/apl/101/9/10.1063/1.4748984
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/9/10.1063/1.4748984
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Drain current vs. back-gate voltage for various temperatures (77 K, 120 K, 200 K, 250 K, and 300 K) for VD  = 0.2 V. Inset: drain current vs. drain voltage with VG  = ±15 V for two different temperatures (120 K and 300 K). Ohmic behavior is obtained for both electrons (VG  > 0) and holes (VG  < 0). Film thickness is of 40 nm.

Image of FIG. 2.
FIG. 2.

Drain current vs. back-gate voltage in semi-log scale for various temperatures (100 K, 140 K, 150 K, and 160 K). Inset: transconductance vs. gate voltage for same temperatures values. VD  = 0.2 V. Film thickness is of 88 nm.

Image of FIG. 3.
FIG. 3.

Measured and theoretical low-field mobility for electrons (a) and holes (b) vs. temperature T for 88 nm and 40 nm Si film thickness. Mobility is decreasing with increasing temperature and denotes that phonon scattering is responsible for mobility reduction in SOI wafer. Error bars are at 20% (calculated from reproducibility measurements not shown here).

Image of FIG. 4.
FIG. 4.

Theoretical and measured subthreshold slope curves (S) as a function of temperature T for 88 nm and 40 nm thick Si film. Error bars are at 18%.

Image of FIG. 5.
FIG. 5.

Theoretical and measured threshold voltage curves (VT ) as a function of temperature T for 88 nm and 40 nm thick Si film. Error bars are at 10%.

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/content/aip/journal/apl/101/9/10.1063/1.4748984
2012-08-30
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Low-temperature pseudo-metal-oxide-semiconductor field-effect transistor measurements on bare silicon-on-insulator wafers
http://aip.metastore.ingenta.com/content/aip/journal/apl/101/9/10.1063/1.4748984
10.1063/1.4748984
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