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(a) Schematic diagram of the device structure. (b) I–V curve between two Al lead wires connected to 2DEG.
(a) Series circuit model comprising a resistor and a capacitor inseries. (b) Parallel circuit model comprising a resistor and a capacitor in parallel. C–V curves of the LAO/STO heterostructure based on (c) the series and (d) parallel circuit models.
Nyquist plots of the LAO/STO heterostructure (a) above and (b) below −1.8 V. Inset of Fig. 3(a): magnified Nyquist plot of the high-frequency range. Calculated capacitance of (c) LAO and (d) STO layers as functions of the applied voltage.
Variation in the capacitance of the LAO/STO heterostructure as a function of the applied voltage. The C–V curve is also compared to CS–V curves on the basis of the series circuit model shown in Fig. 2(c) .
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