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Terahertz responsivity and low-frequency noise in biased silicon field-effect transistors
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View: Figures


Image of FIG. 1.
FIG. 1.

Circuit applied for the low-frequency noise measurements. The dashed square indicates the low-frequency equivalent circuit of an antenna-coupled CMOS detector with its high-frequency equivalent circuit presented in the zoom area. Note: The capacitances Cgd (21 fF) used as an AC shunt at 620 GHz can be neglected below 1 GHz since their impedance at these frequencies exceeds 8 MΩ.

Image of FIG. 2.
FIG. 2.

Response of a CMOS detector to 330-Hz electronically chopped 620-GHz radiation as a function of the DC bias current, measured at gate voltages Vg ranging from 0.5 to 0.7 V. Inset: static I/V characteristics at the same gate voltages. All fitting lines are calculated by Eqs. (1) and (3) with the same set of parameters.

Image of FIG. 3.
FIG. 3.

RC-roll-off-corrected spectral density of the drain voltage fluctuations for near-zero bias (circles), (squares), and (diamonds) for a gate voltage of 0.58 V. Black lines represent fits taking into account thermal noise and excess noise (including both 1/f and generation-recombination noise “gr”), with their relative contributions at indicated by dashed lines. Inset: Measured data . The drain voltage was varied in steps of 20 mV.

Image of FIG. 4.
FIG. 4.

Calculated (dashed lines) and measured (points) SNR values at a modulation frequency of 200 kHz, normalized to the maximum value obtained at  V without bias current. Inset: measured bias dependence of signal (lines) and amplitude of voltage fluctuations (data points) for several modulation frequencies at  V.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Terahertz responsivity and low-frequency noise in biased silicon field-effect transistors