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Illustration depicting the three different biasing schemes used in this study: (a) conventional biasing scheme commonly referred to as DCIV, (b)charge pumping biasing scheme, (c) biasing scheme utilized for the bipolar amplification effect.
This figure illustrates earlier work performed on devices which did and did not receive an NO anneal. The measurements utilized the conventional DCIV biased approach. (a) Comparison of both devices in inversion (+20 V) and (b) in accumulation (−20 V). EDMR amplitude and substrate current as a function of gate bias (c) for a device that did receive an NO anneal and (d) for a device that did not receive an NO anneal. Note that these measurements are ambiguous with regard to the relative concentrations of silicon vacancies at the interface versus silicon vacancies extending some distance below the interface into the SiC.
This figure compares the EDMR responses using SDCP on devices which were identical except one which (b) was processed with an NO anneal. The defects are greatly reduced by the NO anneal.
This figure compares the EDMR responses using BAE biasing scheme on the same devices used to gather the data in Figure 3 . Trace (a) and (b) are taken on devices with precisely identical geometries; however, device (a) did not receive an NO anneal. Trace (c) was taken on a wider channel device (200 μm) which did receive the NO anneal. The additional longer channel device allows the silicon vacancy spectrum to be observed albeit with much lower amplitude. The data illustrated here are consistent with the SDCP results; defects at and very near the interface of technologically relevant devices are effectively reduced by NO anneals.
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