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Integration of on-chip field-effect transistor switches with dopantless Si/SiGe quantum dots for high-throughput testing
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View: Figures


Image of FIG. 1.

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FIG. 1.

Schematic of multiplexing theory and implementation. (a) Schematic of multiplexing of eight accumulation-mode undoped Si/SiGe double quantum dots. The hierarchical structure can be extended straightforwardly to multiplex devices with a number of external lines that grows linearly with . All the DC and RF lines (green) are connected in parallel to every QD (blue). AG represents an electrical bus for five accumulation gate control lines (red) which pass through a series of branching switches blocks (yellows). Control lines are shared by switches with the same label. (b) Schematic of the outlined switch block S2 from (a). The accumulation gate bus (red) is routed through five on-chip FET heterostructures (blue) in parallel that share a common gate electrode (yellow). (c) Cross-section of an on-chip FET switch seen in (b). Source and drain leads come onto the raised mesa of active heterostructure. Electrical connections to the strained silicon well are made through ion-implanted regions (dark blue) on the mesa. Conduction between the source and the drain occurs only when the top gate voltage exceeds a positive threshold at which a 2DEG forms in the Si well. (d) Schematic of the physical layout for four multiplexed, double quantum dot structures using the same color scheme as in (a). The RF lines (dark blue) are kept in a separate bus that never overlaps any of the other buses or itself, to minimize cross-talk. (e) False color image of actual multiplexed, undoped Si/SiGe accumulation mode device using the same color scheme as (a). (f) Same as in (e) without the color modification. The small white box in the lower left indicates where the bottom-left device is located. (g) Optical image of the bottom left device from the boxed region in (f). (h) SEM image of the depletion gates of the quantum device (image acquired partway through the fabrication process). (i) SEM image of a completed quantum device, showing the accumulation gates on top of 80 nm of AlO; the depletion gates from (h) can be observed in the background of the image.

Image of FIG. 2.

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FIG. 2.

(a)–(c) QPC current ( ) as a function of the QPC accumulation gate voltage for the top-left (a), bottom-left (b), and bottom-right (c) dot structures of Fig. 1(a) . Each curve represents a different trial (in the order black, blue, red) after illuminating the sample. While the threshold voltage for accumulation shifts for each trial, the turn-on behavior (the number and sharpness of the peaks in the curves) is qualitatively similar for and characteristic of each specific QPC channel, analogous to a device fingerprint. (d)–(f) QPC current ( ) as a function of the QPC depletion gate voltage for the top-left (a), bottom-left (b), and bottom-right (c) devices, taken at the accumulation gate voltages. Curves have been offset by 0.3 nA for clarity. We again observe that the shape of the curves is similar in each trial for a given device.


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Measuring multiple quantum devices on a single chip increases characterization throughput and enables testing of device repeatability, process yield, and systematic variations in device design. We present a method that uses on-chip field-effect transistor switches to enable multiplexed cryogenic measurements of double quantum dot Si/SiGe devices. Multiplexing enables the characterization of a number of devices that scales exponentially with the number of external wires, a key capability given the significant constraints on cryostat wiring. Using this approach, we characterize three quantum-point contact channels and compare threshold voltages for accumulation and pinch-off voltages during a single cool-down of a dilution refrigerator.


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Scitation: Integration of on-chip field-effect transistor switches with dopantless Si/SiGe quantum dots for high-throughput testing