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Insertion of a Si layer to reduce operation current for resistive random access memory applications
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10.1063/1.4812304
/content/aip/journal/apl/102/25/10.1063/1.4812304
http://aip.metastore.ingenta.com/content/aip/journal/apl/102/25/10.1063/1.4812304
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) Schematic diagram of the two deposited structures. (b) FTIR analyses. (c) Resistive switching behavior comparison between the two devices.

Image of FIG. 2.
FIG. 2.

(a) Conduction mechanism analyses of sample A. (b) The conduction mechanisms in LRS are Ohmic conduction followed by Poole-Frenkel emission. (c) The conduction mechanisms in HRS are a short period of Schottky emission followed by Poole-Frenkel emission.

Image of FIG. 3.
FIG. 3.

(a) Conduction mechanism analyses of sample B. (b) The proposed model of the conduction mechanism in LRS during the set process. (c) Comparison of the energy band diagrams in LRS between these two structures.

Image of FIG. 4.
FIG. 4.

(a) The schematic diagram in LRS, equivalent to two resistances in series. (b) The self-compliance behavior during set process further confirms the existence of the SiO barrier layer.

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/content/aip/journal/apl/102/25/10.1063/1.4812304
2013-06-24
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Insertion of a Si layer to reduce operation current for resistive random access memory applications
http://aip.metastore.ingenta.com/content/aip/journal/apl/102/25/10.1063/1.4812304
10.1063/1.4812304
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