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Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications
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10.1063/1.4788684
/content/aip/journal/apl/102/4/10.1063/1.4788684
http://aip.metastore.ingenta.com/content/aip/journal/apl/102/4/10.1063/1.4788684
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Schematic illustration of the proposed negative resistance device. The device consists of a GNR semiconductor, bottom oxide and bottom gate, and top oxide and top gate, each covering half of the channel. The GNR consists of doped source and drain regions and an intrinsic channel region (as shown in Fig. 2(a) ). The carbon rings are shown for illustrative purposes and do not represent the actual dimensions for the device.

Image of FIG. 2.
FIG. 2.

(a) Schematic top view of the proposed negative resistance device in Fig. 1 and band diagram in GNR for VDS of (b) 0.01 V, (c) 0.13 V, (d) 0.4 V. Source and drain regions are denoted by S and D, respectively. The channel is divided into two regions. TG represents the half of the channel under the top gate, and BG represents the half of the channel over the back gate. Conduction and valence bands are shown by EC and EV , respectively. The potential difference at the two ends of the channel is denoted by ΔΦCh . A schematic illustration of the potential barrier for tunneling is shown in (c) with the shaded region with Λ as the width of the barrier. The quantum well formed at the left side of the channel is shown by QW in (d). Maximum current is observed in (c), where the EF at source and drain aligns approximately with EV at drain and EC at source, respectively. The WF for BG and TG electrodes is 5.2 eV, and for the GNR is 4.5 eV with VTG  = 1.2 V. We can choose a lower value for VTG using a lower WF for the TG electrode.

Image of FIG. 3.
FIG. 3.

Current-voltage (I-V) characteristics of the proposed negative resistance devices. Eg , Ch  = 0.5 eV, and Eg , SD varies between 0.5 eV and 1.1 eV. A peak and a valley point are observed on each curve and marked in Fig. 4 . The gate WF and VTG are the same as in Fig. 2 .

Image of FIG. 4.
FIG. 4.

Current-voltage characteristics for the proposed negative resistance device with two design approaches: variable VBG and constant VBG . In variable VBG design, the BG electrode is tied to the drain electrode, while in the constant VBG design, a constant voltage is applied to the BG. The variable VBG approach offers improved characteristics. The peak and valley points are marked on the curve. The gate WF and VTG are the same as in Fig. 2 .

Image of FIG. 5.
FIG. 5.

I-V characteristics and implementation of a bi-stable static memory cell based on the proposed negative resistance devices. The n-type device corresponds to the pull-down network, and the p-type device corresponds to the pull-up network. An arbitrary value of VDD  = 0.33 V is chosen for the cell. The two curves cross at 3 points marked by stars. The inset shows log10(IDS ) vs. VOUT . The peak current is ∼700 μA/μm for Eg , Ch  = 0.5 eV, and can be further increased by lowering Eg , Ch .

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/content/aip/journal/apl/102/4/10.1063/1.4788684
2013-01-31
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications
http://aip.metastore.ingenta.com/content/aip/journal/apl/102/4/10.1063/1.4788684
10.1063/1.4788684
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