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(a) Output characteristics (IDS-VDS) and (b) transfer characteristics (IDS-VG) of a back-gated ZnO nanowire FET without an FLC layer. The inset shows an optical image of the ZnO nanowire FET with a back-gate configuration.
(a) A schematic view of a back-gated ZnO nanowire FET with an FLC layer. (b) Output characteristics (IDS-VDS) of the FLC-coated ZnO nanowire FET. (c) Hysteretic behaviors of the FLC-coated ZnO nanowire FET (at VDS = 0.1, 0.2, and 1 V). (d) Hysteretic behaviors of the FLC-coated ZnO nanowire FET as a function of the sweep range of gate voltages. Arrows in (c) and (d) indicate gate voltage sweep directions.
(a) Hysteretic behavior of a top-gated ZnO nanowire FET with an FLC layer. The insets show a schematic illustration of positive or negative polarization of an FLC layer induced on a ZnO nanowire depending on gate voltage sweep directions. (b) Reversible, reproducible ON and OFF switching characteristics of a top-gated nanowire device with an FLC layer. (c) Schematic illustrations of a FLC-coated ZnO nanowire FET exhibiting ON and OFF states.
(a) Retention characteristics of the ON and OFF states of a FLC-coated ZnO nanowire FET with a top-gate configuration after the application of a writing pulse (+15 V) and an erasing pulse (−15 V). (b) Schematic diagrams for charge accumulation and depletion in the nanowire channel, corresponding to the ON state and the OFF state, respectively.
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