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ID-VG and corresponding Gm-VG at linear region measurement after HCS for high k/metal gate n-MOSFETs for (a) I/O and (b) SP devices. Insets show the CGD measurement after HCS.
The degradation of ID, Gm, and SS versus stress time extracted for SP and I/O devices under HCS.
ID-VG and corresponding IB-VG measurement showing GIDL current varying with stress time at VD = 2.4 V for (a) I/O and (b) SP devices. Insets show (a) electron trapping decrease (b) hole trapping increase in band-to-band tunneling distance.
Diagram of device profile corresponding to lateral energy band showing (a) electron injection into oxide layer (b) hole injection into high-k layer above overlap at drain side during HCS.
The lateral electric field in T-CAD simulation at Y = 0.99 μm. Inset shows two simulation conditions: (a) electron injection within regions A and Band (b) electron and hole injections at regions A and B, respectively.
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