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Filled-state RT STM images of Mn wires deposited at (a) T sub = −80 °C and (b) T sub = 50 °C. (c) High-resolution STM image after 0.04 ML exposure to Mn showing multiple dimer vacancy complexes as wire seeding sites. (d) STM surface topography after growth of 2 nm of epitaxial Si. STM conditions: −2 V, 0.2 nA.
(a) SIMS depth profile comparison for two substrates, with Mn deposited at T sub = −80 °C [D1] and 50 °C [D2] showing the segregation of Mn and the formation of a Mn δ-layer. (b) XPS spectra revealing the fraction between elemental and oxidized Mn for (b) different Si cap thicknesses and (c) a Mn layer with a 2 nm Si cap as-grown and after chemical removal [SP-BHF-SP] and regrowth of the oxide layer.
High (cyan) and low (blue) frequency C-V characteristics found for MOS devices with the lowest Si [Si2] and Mn D it [Mn4] and the highest Mn D it [Mn2].
Summary of D it values at midgap for all MOS devices investigated in this work. Additional device details are given in the text.
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