Full text loading...
Micrograph of a fabricated CTLM structure on SiO2/Si with s = 25 μm. Magnified area indicates the high quality of the transferred CVD grown graphene.
DC CTLM extrapolation on SiO2/Si and silica glass. Inset: structure layout with relevant dimensions indicated.
Graphene on fused silica. Real part (circles), from bottom to top s = 5–25 μm, and imaginary part (squares), from top to bottom s = 5–25 μm. N.B. scaled ×4.
Equivalent circuit of graphene Corbino structure on fused silica substrate, where and represent inner patch (outer ground plane), respectively.
Graphene on SiO2/Si. Real part (circles), from bottom to top s = 5–25 μm, and imaginary part (squares), from top to bottom s = 5–25 μm. N.B. scaled ×2.
Equivalent circuit of graphene Corbino structure on SiO2/Si substrate, where Rox /Cox and RSi represent the lossy oxide and conductive Si surface, respectively.
Physical outline of the contact interface with the corresponding lumped circuit model. The mean separation dm – g results in a contact capacitance Cc .
Contact resistivity and ring sheet resistance from Eqs. (1) and (2) (data within brackets) based on two sets of CTLM structures each.
Capacitance from curve fitting and extrapolation on fused silica (first row) and SiO2/Si (second row).
Article metrics loading...