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Metal-oxide thin-film transistors patterned by printing
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Image of FIG. 1.
FIG. 1.

Maximum inhibition thickness for ALD ZnO-growth on 200 °C substrates as a function of (a) PMMA and (b) PVP thickness. Different curves correspond to different precursor/purge exposure times. Total ALD cycle time is four times longer (two precursors exposures and two purge exposures).

Image of FIG. 2.
FIG. 2.

Printed patterning of TFTs. (a) Ink-jet printed inhibitor pattern for gate, on an oxide-coated silicon substrate for visual contrast. (b) Inhibitor with SALD-deposited AZO. (c) AZO pattern with inhibitor removed. (d) 3D optical profile of a completed TFT with 70 m long channel. (e) Glass substrate patterned with more than 200 TFTs. (f) Optical microscope image of TFT on glass with width of 400 m and length of 100 m.

Image of FIG. 3.
FIG. 3.

(a) Transfer curves for a typical patterned-by-printing TFT on glass with W/L = 400/100 m and oxide thickness of 500 Å. Linear (V = 0.2 V) and saturation (V = 16 V) curves are shown, along with gate leakage for both curves. Extracted mobility is 3 cm/Vs in the linear and closer to 2.3 cm/Vs for saturation. (b) I-V curves for the same TFT. Saturation is very flat.


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Table I.

A comparison of the maximum inhibition thickness of potential inhibitor materials for ZnO growth at 200 °C.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Metal-oxide thin-film transistors patterned by printing