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Proposal for all-graphene monolithic logic circuits
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10.1063/1.4818462
/content/aip/journal/apl/103/8/10.1063/1.4818462
http://aip.metastore.ingenta.com/content/aip/journal/apl/103/8/10.1063/1.4818462

Figures

Image of FIG. 1.
FIG. 1.

(a) The atomic structure of graphene. Armchair (ac) and zigzag (zz) are two different chiralities; (b) band structure of graphene; (c) band structure of armchair-GNR (ac-GNR); (d–f) Schematics showing proposed fabrication steps of an “all-graphene” circuit (inverter chain): (d) monolayer graphene sheet; (e) graphene interconnects and GNRs patterned by lithography; source and drain regions are doped; (f) all-graphene circuit after deposition and patterning of metal and dielectric; (g) Circuit schematic of (f). Inverter 2 is double-sized using two GNR channels (hence fan-out of Inverter 1 = 2).

Image of FIG. 2.
FIG. 2.

(a) - curves of P-i-N and P-i-N GNR-TFETs; Inset figure in (a) shows the device structure; (b–d) Band diagrams of (b) OFF state; (c) ON state and (d) ON state with tunneling at drain-channel junction. The - points corresponding to (b–d) are marked in (a).

Image of FIG. 3.
FIG. 3.

(a) Schematic showing the simulated drain-interconnect-drain region; (b, d) Local density of states (LDOS) and band diagrams of the simulated region in (a) with: (b) high doped drains (|Φ| = 0.8 eV) and (d) low doped drains (|Φ| = 0.5 eV). (c, e) Transmission spectrum (()) of (b) and (d), respectively. TW is transmission window. (f, g) I-V curves of D-i-D regions for different drain doping levels: (f)  = 6; (g)  = 40, where is the number of C atoms along the width of GNR. and denote the voltage and current from PTFET drain to NTFET drain, respectively. |Φ| is the Fermi potential in the drain regions. Note that both |Φ| and affect TW.

Image of FIG. 4.
FIG. 4.

Band diagram of an inverter showing (a) rising of output ( rises from low to high; dashed lines and solid lines represent bands before and after rising of output, respectively; and (b) falling of output ( falls from high to low; dashed lines represent bands before discharging and solid lines are discharged bands) of the output node ( ); red arrows represent current directions.

Image of FIG. 5.
FIG. 5.

(a) Inverter VTCs for all-graphene circuits and 22 nm-CMOS under different . Inset plot is zoom of (a) at  ∼ 0–0.1 V. (b) definitions of gain, , , , and for inverters.

Image of FIG. 6.
FIG. 6.

Plot of output current (the current flowing to output node) vs. and static leakage current vs. .

Image of FIG. 7.
FIG. 7.

Static leakage power for 22 nm all-graphene inverters with different widths, in comparison with 22 nm-CMOS inverters with default threshold voltages, plotted as a function of .

Tables

Generic image for table
Table I.

Normalized SNM (SNM/) and inverter gain vs. . Note: When |Gain| < 1, SNM does not exist according to the definition in Figure 5(b) .

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/content/aip/journal/apl/103/8/10.1063/1.4818462
2013-08-22
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Proposal for all-graphene monolithic logic circuits
http://aip.metastore.ingenta.com/content/aip/journal/apl/103/8/10.1063/1.4818462
10.1063/1.4818462
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