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(a) The atomic structure of graphene. Armchair (ac) and zigzag (zz) are two different chiralities; (b) band structure of graphene; (c) band structure of armchair-GNR (ac-GNR); (d–f) Schematics showing proposed fabrication steps of an “all-graphene” circuit (inverter chain): (d) monolayer graphene sheet; (e) graphene interconnects and GNRs patterned by lithography; source and drain regions are doped; (f) all-graphene circuit after deposition and patterning of metal and dielectric; (g) Circuit schematic of (f). Inverter 2 is double-sized using two GNR channels (hence fan-out of Inverter 1 = 2).
(a) V GS -I DS curves of P+-i-N+ and P+-i-N GNR-TFETs; Inset figure in (a) shows the device structure; (b–d) Band diagrams of (b) OFF state; (c) ON state and (d) ON state with tunneling at drain-channel junction. The V GS -I DS points corresponding to (b–d) are marked in (a).
(a) Schematic showing the simulated drain-interconnect-drain region; (b, d) Local density of states (LDOS) and band diagrams of the simulated region in (a) with: (b) high doped drains (|eΦ P,N | = 0.8 eV) and (d) low doped drains (|eΦ P,N | = 0.5 eV). (c, e) Transmission spectrum (T(E)) of (b) and (d), respectively. TW is transmission window. (f, g) I-V curves of D-i-D regions for different drain doping levels: (f) NW = 6; (g) NW = 40, where NW is the number of C atoms along the width of GNR. VF and IF denote the voltage and current from PTFET drain to NTFET drain, respectively. |eΦ P,N | is the Fermi potential in the drain regions. Note that both |eΦ P,N | and VF affect TW.
Band diagram of an inverter showing (a) rising of output (V out rises from low to high; dashed lines and solid lines represent bands before and after rising of output, respectively; and (b) falling of output (V out falls from high to low; dashed lines represent bands before discharging and solid lines are discharged bands) of the output node (V out ); red arrows represent current directions.
(a) Inverter VTCs for all-graphene circuits and 22 nm-CMOS under different VDD . Inset plot is zoom of (a) at Vin ∼ 0–0.1 V. (b) definitions of gain, VIH , VIL , VOL , and VOH for inverters.
Plot of output current Iout (the current flowing to output node) vs. VDD and static leakage current Ileak vs. VDD .
Static leakage power for 22 nm all-graphene inverters with different widths, in comparison with 22 nm-CMOS inverters with default threshold voltages, plotted as a function of VDD .
Normalized SNM (SNM/VDD ) and inverter gain vs. VDD . Note: When |Gain| < 1, SNM does not exist according to the definition in Figure 5(b) .
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